Vivado AXI4-Stream 接口解读
理论学习需结合实际仿真验证。通过实际对比，发现理论与实现存在差异，现结合实践重新梳理 AXI 理论知识。
什么是 AXI4？
AXI 表示 Advanced eXtensible Interface（高级可扩展接口），它是由 Arm 定义的接口协议，包含在'高级微控制器总线架构 AMBA'标准中。
AXI4 接口 (AMBA 4.0) 分 3 种类型：
- AXI4 (AXI4-Full)：用于满足高性能存储器映射需求。
- AXI4-Lite：用于简单的低吞吐量存储器映射通信（例如，往来于状态寄存器的通信）。
- AXI4-Stream：用于高速流传输数据。
AXI-Stream
先从最简单的入手，接口如下：
| 类别 (Category) | 信号 (Signal) | 来源 (Source) | 描述 (Description) |
|---|---|---|---|
| 系统类 (System) | ACLK | Clock source | The global clock signal. All signals are sampled on the rising edge of ACLK. |
| ARESETn | Reset source | The global reset signal. ARESETn is active-LOW. | |
| 传输数据类 (Data Transfer) | TVALID | Master | TVALID indicates that the master is driving a valid transfer. A transfer takes place when both TVALID and TREADY are asserted. |
| TREADY | Slave | TREADY indicates that the slave can accept a transfer in the current cycle. | |
| TDATA[(8n-1):0] | Master | TDATA is the primary payload that is used to provide the data that is passing across the interface. The width of the data payload is an integer number of bytes. | |
| 数据修饰类 (Data Qualifier) | TSTRB[(n-1):0] | Master | TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte. |
| TKEEP[(n-1):0] | Master | TKEEP is the byte qualifier that indicates whether the content of the associated byte of is processed as part of the data stream. Associated bytes that have the byte qualifier deasserted are null bytes and can be removed from the data stream. |
