ZU47DR RFdc Linux 驱动编译与使用指南

综述由AI生成基于 ZynqUltraScale+ RFSoC ZU47DR 芯片在嵌入式 Linux 环境下配置 RFdc 驱动的完整流程。通过 PetaLinux 编译系统镜像并启用 rfdc 支持，结合 Vitis 创建应用程序工程，最终在板卡上验证了 DAC/ADC 的多 Tile 同步及增益校正功能。实验确认了内核驱动加载正常，API 接口可用，实现了射频数据转换器的基本性能测试。

涅槃凤凰发布于 2026/3/16更新于 2026/5/322 浏览

前言

ZynqUltraScale+ RFSoC ZU47DR，在一款芯片内集成射频直接采样数据转换器、FPGA 逻辑、完整的 ARM 处理器子系统和高速收发器等。本例程使用 petalinux2022.1 编译系统镜像，进行本次实验前请先了解 petalinux 的编译流程。RFdc 驱动接口在 Linux 和裸跑下一致，调用的 API 可参考裸跑下的实现。本次实验的核心目的在于验证 xczu47d 芯片的 RF Data Converter 子系统在嵌入式 Linux 环境下的工作状态、功能完整性和基本性能表现，确认 Linux 内核能够正确识别并加载 Xilinx 提供的 RFdc 硬件驱动模块，验证用户空间与 RFdc 硬件交互所需的软件库（如 XRFdc 库）及依赖（libmetal 等）安装配置正确，API 调用接口可用等其他功能。

测试平台与环境

系统：Windows 10

开发工具：Vivado 2022.1 + Vitis 2022.1 + PetaLinux 2022.1 (Ubuntu 22.04)

板卡：自制板卡

FPGA 工程搭建

FPGA 与裸跑下工程搭建一致。

构建 Linux 镜像

在上节中我们已经完成了硬件工程并导出了硬件描述文件（XSA），本节我们将编译 Linux 镜像和带有 RFdc 驱动的文件系统。首先我们创建一个 petalinux 工程，并导入硬件描述文件。

petalinux-create -t project --template zynqMP -n rfdc_image
cd rfdc_image
petalinux-config --get-hw-description=<path to XSA>

然后复制 meta-petalinux/recipes-bsp 中的内容到工程目录的 project-spec/meta-user/recipes-bsp 中。

然后在 meta-user/conf/user-rootfsconfig 文件中添加如下内容。

然后使用 petalinux-config -c rootfs，在根文件系统的配置中添加 rfdc 的支持。

petalinux-config -c rootfs

User Packages ->

[*] rfdc
[*] rfdc-read-write
[*] rfdc-selftest

编辑当前 petalinux 工程目录下的 project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi 文件。

然后构建镜像并生成可启动的 BOOT.BIN 文件。

petalinux-build
petalinux-package --boot --fpga --u-boot

编译完成后将 BOOT.BIN、boot.scr 和 image.ub 文件复制到 SD 卡中，将板卡设置为 SD 卡启动，打开串口调试终端，串口配置为：波特率 115200，8 数据位，1 开始，1 停止，即可进入 Linux 系统。系统默认用户为 petalinux。

创建 Linux 应用程序

上节我们已经生成了 Linux 的启动镜像，本节我们将在 Vitis 中编译 rfdc 的例程。我们先要在 petalinux 的工程中生成目标的系统根目录用以 Vitis 中的代码编译。

petalinux-build --sdk
petalinux-package --sysroot

编译完成后在 images/linux 目录下可见 sdk 目录。

将 sdk 目录复制到 Vitis 的目录中，新建 Linux 的 Platform 工程，将 sysroot Directory 设置为 sdk\sysroots\cortexa72-cortexa53-xilinx-linux 目录。

然后在 Vitis 中新建应用程序，File → New → Application Project，Sysroot path 选择 sdk\sysroots\cortexa72-cortexa53-xilinx-linux。

然后添加 RFdc 的例程代码，在工程配置中添加库。

最后编译即可生成可执行文件。

板卡运行验证

将上节生成的可执行文件传输到板卡上，添加可执行权限，然后 ./ 即可运行。

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rfdcimage:~/test$ sudo ./rf_linux.elf Password: RFdc linux Example Test metal: info: metal_linux_dev_open: checking driver vfio-platform,80000000.usp_rf_data_converter,(null) metal: info: metal_uio_dev_open: No IRQ for device 80000000.usp_rf_data_converter. tile=0,block=0,XRFdc_SetDACVOP,Status=0 tile=0,block=0,Attenuation=0.000000,Status=0 tile=0,block=1,XRFdc_SetDACVOP,Status=0 tile=0,block=1,Attenuation=0.000000,Status=0 tile=1,block=0,XRFdc_SetDACVOP,Status=0 tile=1,block=0,Attenuation=0.000000,Status=0 tile=1,block=1,XRFdc_SetDACVOP,Status=0 tile=1,block=1,Attenuation=0.000000,Status=0 tile=2,block=0,XRFdc_SetDACVOP,Status=0 tile=2,block=0,Attenuation=0.000000,Status=0 tile=2,block=1,XRFdc_SetDACVOP,Status=0 tile=2,block=1,Attenuation=0.000000,Status=0 tile=3,block=0,XRFdc_SetDACVOP,Status=0 tile=3,block=0,Attenuation=0.000000,Status=0 tile=3,block=1,XRFdc_SetDACVOP,Status=0 tile=3,block=1,Attenuation=0.000000,Status=0 DAC converter samplerate=5000000000Hz ADC converter samplerate=2500000000Hz DAC NCO frequency of Tile#0 Block0 is set to -4500.000000 DAC NCO frequency of Tile#0 Block1 is set to -4500.000000 DAC NCO frequency of Tile#1 Block0 is set to -4500.000000 DAC NCO frequency of Tile#1 Block1 is set to -4500.000000 DAC NCO frequency of Tile#2 Block0 is set to -4500.000000 DAC NCO frequency of Tile#2 Block1 is set to -4500.000000 DAC NCO frequency of Tile#3 Block0 is set to -4500.000000 DAC NCO frequency of Tile#3 Block1 is set to -4500.000000 ADC NCO frequency of Tile#0 Block0 is set to -1200.000000 ADC NCO frequency of Tile#0 Block1 is set to -1200.000000 ADC NCO frequency of Tile#1 Block0 is set to -1200.000000 ADC NCO frequency of Tile#1 Block1 is set to -1200.000000 ADC NCO frequency of Tile#2 Block0 is set to -1200.000000 ADC NCO frequency of Tile#2 Block1 is set to -1200.000000 ADC NCO frequency of Tile#3 Block0 is set to -1200.000000 ADC NCO frequency of Tile#3 Block1 is set to -1200.000000 tile=0,block=0,EnableGain=0 tile=0,block=0,GainCorrectionFactor=0.000000 tile=0,block=1,EnableGain=0 tile=0,block=1,GainCorrectionFactor=0.000000 tile=1,block=0,EnableGain=0 tile=1,block=0,GainCorrectionFactor=0.000000 tile=1,block=1,EnableGain=0 tile=1,block=1,GainCorrectionFactor=0.000000 tile=2,block=0,EnableGain=0 tile=2,block=0,GainCorrectionFactor=0.000000 tile=2,block=1,EnableGain=0 tile=2,block=1,GainCorrectionFactor=0.000000 tile=3,block=0,EnableGain=0 tile=3,block=0,GainCorrectionFactor=0.000000 tile=3,block=1,EnableGain=0 tile=3,block=1,GainCorrectionFactor=0.000000 tile=0,block=0,EnableGain=1,Status=0 tile=0,block=0,GainCorrectionFactor=1.000000 tile=0,block=1,EnableGain=1,Status=0 tile=0,block=1,GainCorrectionFactor=1.000000 tile=1,block=0,EnableGain=1,Status=0 tile=1,block=0,GainCorrectionFactor=1.000000 tile=1,block=1,EnableGain=1,Status=0 tile=1,block=1,GainCorrectionFactor=1.000000 tile=2,block=0,EnableGain=1,Status=0 tile=2,block=0,GainCorrectionFactor=1.000000 tile=2,block=1,EnableGain=1,Status=0 tile=2,block=1,GainCorrectionFactor=1.000000 tile=3,block=0,EnableGain=1,Status=0 tile=3,block=0,GainCorrectionFactor=1.000000 tile=3,block=1,EnableGain=1,Status=0 tile=3,block=1,GainCorrectionFactor=1.000000 tile=0,block=0,EnableGain=0 tile=0,block=0,GainCorrectionFactor=0.000000 tile=0,block=1,EnableGain=0 tile=0,block=1,GainCorrectionFactor=0.000000 tile=1,block=0,EnableGain=0 tile=1,block=0,GainCorrectionFactor=0.000000 tile=1,block=1,EnableGain=0 tile=1,block=1,GainCorrectionFactor=0.000000 tile=2,block=0,EnableGain=0 tile=2,block=0,GainCorrectionFactor=0.000000 tile=2,block=1,EnableGain=0 tile=2,block=1,GainCorrectionFactor=0.000000 tile=3,block=0,EnableGain=0 tile=3,block=0,GainCorrectionFactor=0.000000 tile=3,block=1,EnableGain=0 tile=3,block=1,GainCorrectionFactor=0.000000 tile=0,block=0,EnableGain=1,Status=0 tile=0,block=0,GainCorrectionFactor=1.000000 tile=0,block=1,EnableGain=1,Status=0 tile=0,block=1,GainCorrectionFactor=1.000000 tile=1,block=0,EnableGain=1,Status=0 tile=1,block=0,GainCorrectionFactor=1.000000 tile=1,block=1,EnableGain=1,Status=0 tile=1,block=1,GainCorrectionFactor=1.000000 tile=2,block=0,EnableGain=1,Status=0 tile=2,block=0,GainCorrectionFactor=1.000000 tile=2,block=1,EnableGain=1,Status=0 tile=2,block=1,GainCorrectionFactor=1.000000 tile=3,block=0,EnableGain=1,Status=0 tile=3,block=0,GainCorrectionFactor=1.000000 tile=3,block=1,EnableGain=1,Status=0 tile=3,block=1,GainCorrectionFactor=1.000000 === RFdc Initialized - Running Multi-tile Sync div=-1775560512=== === Run DAC Sync === metal: info: DTC Scan PLL metal: info: DAC2: 0000000000000000001132220000000000000000000000000000000011322200#000000000000*00000000000000001122220000000000000000000000000000 metal: info: DTC Scan T1 metal: info: DAC2: 0000000000000000001132220000000000000000000000000000000011322200#000000000000*00000000000000001122220000000000000000000000000000 metal: info: DAC0: 0000000000000000001122220000000000000000000000000000000113222000000000000000*#00000000000000111322200000000000000000000000000000 metal: info: DAC1: 00000000000000000000113222000000000000000000000000000000001132200000000000000#*0000000000000000111222000000000000000000000000000 metal: info: DAC3: 00000000000000000011322200000000000000000000000000000000111222000000000000000*00000000000000011132220000000000000000000000000000 metal: info: DAC0: Marker: - 35, 0 metal: info: DAC1: Marker: - 35, 0 metal: info: DAC2: Marker: - 35, 0 metal: info: DAC3: Marker: - 35, 0 metal: info: SysRef period in terms of DAC T1s = 1600 metal: info: DAC target latency = 700 INFO : DAC Multi-Tile-Sync completed successfully === Run ADC Sync === metal: info: DTC Scan PLL metal: info: ADC2: 00000000011222000000000000001122220000000000000113222000000*0000#011122200000000000001132220000000000000011322200000000000001132 metal: info: DTC Scan T1 metal: info: ADC2: 0000000000000000000001122220000000000000000000000000000000000*00#000000000000000000000000000000001122220000000000000000000000000 metal: info: ADC0: 000000000000000001112220000000000000000000000000000000000*000#000000000000000000000000000000011322200000000000000000000000000000 metal: info: ADC1: 000000000000000000001132200000000000000000000000000000000000*#000000000000000000000000000000000011322000000000000000000000000000 metal: info: ADC3: 000000000000000000001112220000000000000000000000000000000000*#000000000000000000000000000000000011122200000000000000000000000000 metal: info: ADC0: Marker: - 11, 3 metal: info: ADC1: Marker: - 11, 3 metal: info: ADC2: Marker: - 11, 3 metal: info: ADC3: Marker: - 11, 3 metal: info: SysRef period in terms of ADC T1s = 800 metal: info: ADC target latency = 116 INFO : ADC Multi-Tile-Sync completed successfully metal: warning: Inverse Sinc mode and Nyquist Zone are incompatible for DAC 0 block 0 in XRFdc_SetInvSincFIR metal: warning: Inverse Sinc mode and Nyquist Zone are incompatible for DAC 0 block 2 in XRFdc_SetInvSincFIR metal: warning: Inverse Sinc mode and Nyquist Zone are incompatible for DAC 1 block 0 in XRFdc_SetInvSincFIR metal: warning: Inverse Sinc mode and Nyquist Zone are incompatible for DAC 1 block 2 in XRFdc_SetInvSincFIR metal: warning: Inverse Sinc mode and Nyquist Zone are incompatible for DAC 2 block 0 in XRFdc_SetInvSincFIR metal: warning: Inverse Sinc mode and Nyquist Zone are incompatible for DAC 2 block 2 in XRFdc_SetInvSincFIR metal: warning: Inverse Sinc mode and Nyquist Zone are incompatible for DAC 3 block 0 in XRFdc_SetInvSincFIR metal: warning: Inverse Sinc mode and Nyquist Zone are incompatible for DAC 3 block 2 in XRFdc_SetInvSincFIR === Multi-Tile Sync Report === DAC0: Latency(T1) =700, Adjusted DelayOffset(T5) = 0 DAC1: Latency(T1) =700, Adjusted DelayOffset(T5) = 0 DAC2: Latency(T1) =700, Adjusted DelayOffset(T5) = 0 DAC3: Latency(T1) =700, Adjusted DelayOffset(T5) = 0 ADC0: Latency(T1) =116, Adjusted DelayOffset(T2) = 0 ADC1: Latency(T1) =116, Adjusted DelayOffset(T2) = 0 ADC2: Latency(T1) =116, Adjusted DelayOffset(T2) = 0 ADC3: Latency(T1) =116, Adjusted DelayOffset(T2) = 0 The sw lasted build at 20:42:02 Aug 18 2025 Rfdc config succcess!!! Successfully ran linux Example Test

ZU47DR RFdc Linux 驱动编译与使用指南

前言

测试平台与环境

FPGA 工程搭建

构建 Linux 镜像

创建 Linux 应用程序

板卡运行验证

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参考资料

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ZU47DR RFdc Linux 驱动编译与使用指南

前言

测试平台与环境

FPGA 工程搭建

构建 Linux 镜像

创建 Linux 应用程序

板卡运行验证

微信扫一扫，关注极客日志

更多推荐文章

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参考资料

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