FPGA 开发环境搭建：Quartus II 13.1 与 ModelSim 安装配置指南 | 极客日志

FPGA 开发环境搭建：Quartus II 13.1 与 ModelSim 安装配置指南 | 极客日志

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity div is
    port(clk : in std_logic;
         rst : in std_logic;
         clkout : out std_logic);
end div;

architecture rtl of div is
    constant n : integer range 0 to 10 := 6; -- 分频系数
    signal clk_p : std_logic;
    signal clk_n : std_logic;
    signal cnt_p : integer range 0 to n;
    signal cnt_n : integer range 0 to n;
begin
    process(clk_p, clk_n)
    begin
        if((n mod 2) = 0) then
            clkout <= clk_p;
        else
            clkout <= clk_p or clk_n;
        end if;
    end process;

    process(clk, rst)
    begin
        if(rst = '0') then
            cnt_p <= 0;
        elsif(clk'event and clk = '1') then
            if(cnt_p = n-1) then
                cnt_p <= 0;
            else
                cnt_p <= cnt_p + 1;
            end if;
        end if;
    end process;

    process(clk, rst)
    begin
        if(rst = '0') then
            clk_p <= '0';
        elsif(clk'event and clk = '1') then
            if (cnt_p < (n/2)) then
                clk_p <= '1';
            else
                clk_p <= '0';
            end if;
        end if;
    end process;

    process(clk, rst)
    begin
        if(rst = '0') then
            cnt_n <= 0;
        elsif(clk'event and clk = '0') then
            if(cnt_n = n-1) then
                cnt_n <= 0;
            else
                cnt_n <= cnt_n + 1;
            end if;
        end if;
    end process;

    process(clk, rst)
    begin
        if(rst = '0') then
            clk_n <= '0';
        elsif(clk'event and clk = '0') then
            if (cnt_n < (n/2)) then
                clk_n <= '1';
            else
                clk_n <= '0';
            end if;
        end if;
    end process;
end rtl;