Synopsys：默认报告精度(report_default_significant_digits变量)

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Synopsyshttps://blog.ZEEKLOG.net/weixin_45791458/category_12812219.html?spm=1001.2014.3001.5482

        在使用report_timing之类的报告命令时，可以使用-significant_digits选项指定报告的精度，在不使用该选项的情况下，命令使用由report_default_significant_digits变量指定的默认精度进行报告。

        对于不同的工具，该变量的默认值和取值范围略有差别，如下所示。

Design Compiler：默认值为-1（表示使用命令特定的默认值），取值范围为-1到13。

IC Compiler：默认值为-1（表示使用命令特定的默认值），取值范围为-1到13。

PrimeTime：默认值为2，取值范围为0到13。

PrimePower：默认值为2，取值范围为0到13。

Fusion Compiler：默认值为2，取值范围为0到13。

IC Compiler II：默认值为2，取值范围为0到13。

NanoTime：默认值为3，取值范围为0到13。

RTL Architect：默认值为2，取值范围为0到13。

        并非所有报告命令都支持这个变量，具体需要查看命令手册。

        下面展示了report_default_significant_digits变量在PrimeTime中的使用方式。

pt_shell> report_timing **************************************** Report : timing -path_type full -delay_type max -max_paths 1 -sort_by slack Design : ORCA Version: O-2018.06-SP1 Date : Mon Jul 28 18:47:46 2025 **************************************** Startpoint: I_ORCA_TOP/I_PCI_CORE/pad_en_reg (rising edge-triggered flip-flop clocked by PCI_CLK) Endpoint: pad[1] (output port clocked by PCI_CLK) Path Group: PCI_CLK Path Type: max Min Clock Paths Derating Factor : 0.90 Point Incr Path ------------------------------------------------------------------------------ clock PCI_CLK (rise edge) 0.00 0.00 clock network delay (propagated) 3.63 3.63 I_ORCA_TOP/I_PCI_CORE/pad_en_reg/CP (sdcrq1) 0.00 3.63 r I_ORCA_TOP/I_PCI_CORE/pad_en_reg/Q (sdcrq1) 0.40 & 4.03 r U7/ZN (inv0d1) 0.07 & 4.10 f U62/ZN (inv0d1) 0.04 & 4.14 r U63/Z (or02d7) 0.27 & 4.41 r U63ASTipoInst495/Z (bufbdk) 0.31 & 4.71 r U63ASTipoInst494/Z (bufbda) 3.80 & 8.51 r pad_iopad_1/PAD (pc3b03) 6.12 H 14.63 r pad[1] (inout) 0.05 14.68 r data arrival time 14.68 clock PCI_CLK (rise edge) 15.00 15.00 clock network delay (propagated) 0.00 15.00 clock reconvergence pessimism 0.00 15.00 output external delay -4.00 11.00 data required time 11.00 ------------------------------------------------------------------------------ data required time 11.00 data arrival time -14.68 ------------------------------------------------------------------------------ slack (VIOLATED) -3.68 pt_shell> set_app_var report_default_significant_digits 4 pt_shell> report_timing **************************************** Report : timing -path_type full -delay_type max -max_paths 1 -sort_by slack Design : ORCA Version: O-2018.06-SP1 Date : Mon Jul 28 18:49:21 2025 **************************************** Startpoint: I_ORCA_TOP/I_PCI_CORE/pad_en_reg (rising edge-triggered flip-flop clocked by PCI_CLK) Endpoint: pad[1] (output port clocked by PCI_CLK) Path Group: PCI_CLK Path Type: max Min Clock Paths Derating Factor : 0.9000 Point Incr Path ------------------------------------------------------------------------------ clock PCI_CLK (rise edge) 0.0000 0.0000 clock network delay (propagated) 3.6278 3.6278 I_ORCA_TOP/I_PCI_CORE/pad_en_reg/CP (sdcrq1) 0.0000 3.6278 r I_ORCA_TOP/I_PCI_CORE/pad_en_reg/Q (sdcrq1) 0.4038 & 4.0315 r U7/ZN (inv0d1) 0.0660 & 4.0976 f U62/ZN (inv0d1) 0.0424 & 4.1400 r U63/Z (or02d7) 0.2692 & 4.4092 r U63ASTipoInst495/Z (bufbdk) 0.3057 & 4.7149 r U63ASTipoInst494/Z (bufbda) 3.7983 & 8.5132 r pad_iopad_1/PAD (pc3b03) 6.1185 H 14.6317 r pad[1] (inout) 0.0484 14.6801 r data arrival time 14.6801 clock PCI_CLK (rise edge) 15.0000 15.0000 clock network delay (propagated) 0.0000 15.0000 clock reconvergence pessimism 0.0000 15.0000 output external delay -4.0000 11.0000 data required time 11.0000 ------------------------------------------------------------------------------ data required time 11.0000 data arrival time -14.6801 ------------------------------------------------------------------------------ slack (VIOLATED) -3.6801 pt_shell> report_timing -significant_digits 5 **************************************** Report : timing -path_type full -delay_type max -max_paths 1 -sort_by slack Design : ORCA Version: O-2018.06-SP1 Date : Mon Jul 28 18:49:52 2025 **************************************** Startpoint: I_ORCA_TOP/I_PCI_CORE/pad_en_reg (rising edge-triggered flip-flop clocked by PCI_CLK) Endpoint: pad[1] (output port clocked by PCI_CLK) Path Group: PCI_CLK Path Type: max Min Clock Paths Derating Factor : 0.90000 Point Incr Path ------------------------------------------------------------------------------ clock PCI_CLK (rise edge) 0.00000 0.00000 clock network delay (propagated) 3.62777 3.62777 I_ORCA_TOP/I_PCI_CORE/pad_en_reg/CP (sdcrq1) 0.00000 3.62777 r I_ORCA_TOP/I_PCI_CORE/pad_en_reg/Q (sdcrq1) 0.40376 & 4.03154 r U7/ZN (inv0d1) 0.06603 & 4.09757 f U62/ZN (inv0d1) 0.04243 & 4.13999 r U63/Z (or02d7) 0.26920 & 4.40919 r U63ASTipoInst495/Z (bufbdk) 0.30573 & 4.71492 r U63ASTipoInst494/Z (bufbda) 3.79833 & 8.51324 r pad_iopad_1/PAD (pc3b03) 6.11847 H 14.63171 r pad[1] (inout) 0.04841 14.68012 r data arrival time 14.68012 clock PCI_CLK (rise edge) 15.00000 15.00000 clock network delay (propagated) 0.00000 15.00000 clock reconvergence pessimism 0.00000 15.00000 output external delay -4.00000 11.00000 data required time 11.00000 ------------------------------------------------------------------------------ data required time 11.00000 data arrival time -14.68012 ------------------------------------------------------------------------------ slack (VIOLATED) -3.68012