FPGA 与 STM32 的 FMC 通信协议
// fsmc read / write ep4ce6 demo module
module fsmc(
input [2:0] ab, // address
inout [15:0] db, // data
input wrn, // write
input rdn, // read
input resetn, // reset
input csn, // chip select
input [15:0] ina, // input data a
input [15:0] inb, // input data b
input [15:0] inc, // input data c
input [15:0] ind, // input data d
input [15:0] ine, // input data e
input [15:0] inf, // input data f
input [15:0] ing, // input data g
input [15:0] inh, // input data h
output reg [15:0] outa,
output reg [15:0] outb,
output reg [15:0] outc,
output reg [15:0] outd,
output reg [15:0] oute,
output reg [15:0] outf,
output reg [15:0] outg,
output reg [15:0] outh
);
wire rd;
wire wr;
reg [15:0] indata;
assign rd = !(csn & rdn); // get rd pulse
assign wr = !(csn & wrn); // get wr pulse
assign db = rd ? indata : 16'bz; // write data
// write data: select 8 spaces based on address lines, each space 16 bits
always @(negedge wr or negedge resetn) begin
if (!resetn) begin
outa <= 16'h0000;
outb <= 16'h0000;
outc <= 16'h0000;
outd <= 16'h0000;
oute <= 16'h0000;
outf <= 16'h0000;
outg <= 16'h0000;
outh <= 16'h0000;
end else begin
case (ab)
3'b000: outa <= db;
3'b001: outb <= db;
3'b010: outc <= db;
3'b011: outd <= db;
3'b100: oute <= db;
3'b101: outf <= db;
3'b110: outg <= db;
3'b111: outh <= db;
default: ;
endcase
end
end
// read data: select 8 spaces based on address lines, each space 16 bits
always @(rd or !resetn) begin
if (!resetn) indata <= 16'h0000;
else begin
case (ab)
3'b000: indata <= ina;
3'b001: indata <= inb;
3'b010: indata <= inc;
3'b011: indata <= ind;
3'b100: indata <= ine;
3'b101: indata <= inf;
3'b110: indata <= ing;
3'b111: indata <= inh;
default: ;
endcase
end
end
endmodule
FMC 通信协议说明
这里的 FMC_A0 表示地址线。共有 13 位地址线和 16 位数据线，行地址与列地址公用：作为行地址时使用了 012 位，作为列地址时使用了 08 位。
主要信号定义如下：
- FMC_SDNWE：低电平时写，高电平时读；
- FMC_SDNCAS：列地址选通信号，低电平有效；
